-------------------------------------------------------------------------------
--
-- Title       : ALU
-- Design      : ALU
-- Author      : Microsoft
-- Company     : Microsoft
--
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--
-- File        : ALU.vhd
-- Generated   : Tue Nov 22 14:02:19 2011
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description : 
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {ALU} architecture {ALU}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.constants.all;

entity aluTb is 
end entity aluTb;

architecture tb of aluTb is 
component ALU is 
	port(
	instr:          in  AluOpType;  	--op-code of instruction to be carried out
	aIn :		in  std_logic_vector(31 downto 0);	--first Operand
	bIn :		in  std_logic_vector(31 downto 0);	--second Operand
	result:     	out std_logic_vector(31 downto 0);	--culculation result
	flagZero:      	out std_logic;	 			-- TO DO 
	flagNeg:        out std_logic;	 			-- result is negative	 
	flagOverflow:	out std_logic);
	
end  component ALU;

--}} End of automatically maintained section

signal	instr: AluOpType;  	--op-code of instruction to be carried out
signal	aIn : std_logic_vector(31 downto 0);	--first Operand
signal	bIn : std_logic_vector(31 downto 0);	--second Operand
signal	result: std_logic_vector(31 downto 0);	--culculation result
signal	flagZero: std_logic;	 			-- TO DO 
signal	flagNeg:  std_logic;	 		-- result is negative	 
signal	flagOverflow: std_logic;
	

begin
uut: ALU port map
	(instr, aIn, bIn, result, flagZero, flagNeg, flagOverflow);

driverP: process is
  begin
    aIn <= x"11000111";
    bIn <= x"00001001";
    instr <= ALU_SHIFT_R;
    wait for 10 ns;
    wait;
  end process driverP;
end architecture tb;
